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Sam Zeloof’s chips are not finely etched printed circuit boards: they are silicon integrated circuits built with photolithography, doped silicon, oxide layers and metal interconnects. His home laboratory produced a six-FET amplifier chip called the Z1 and, later, a reported 1,200-transistor array in the Z2 project. The work shows that small functional ICs can be made outside a commercial fab, but not with an ordinary PCB etching kit—and not with commercial-fab repeatability.
How is making an IC different from etching a PCB?
A conventional PCB starts with copper bonded to an insulating board. Etching removes selected copper to leave conductive paths. An integrated circuit is built on a silicon wafer: fabrication patterns insulating oxide, doped regions in the silicon and deposited metal layers to create transistors and connect them into a circuit.
That distinction matters more than the apparent similarity of using a pattern and an etch. Zeloof’s work combined wafer preparation, oxidation, doping, photolithography, etching, vacuum deposition and electrical testing. It was semiconductor fabrication in a family-garage laboratory, not PCB etching reduced to a finer scale. Hackaday’s account describes the progression from homemade diodes and MOSFETs to the Z1, which it characterizes as a hobbyist photolithography-made IC.
What did Zeloof build, and what worked?
Zeloof describes the Z1 as a “homemade (lithographically-fabricated) integrated circuit” and a PMOS dual differential amplifier. His project notes specify six FETs in its original design. The Z2 project advanced to a polysilicon-gate process and substantially larger transistor arrays.
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| Measure | Z1 | Z2 |
|---|---|---|
| Circuit or process | PMOS dual differential amplifier; aluminum-gate process, according to Zeloof’s project notes. | Polysilicon-gate NMOS process, according to Zeloof’s 2021 update. |
| Transistors | Six FETs in the original amplifier design (Zeloof’s project notes). | 100 transistors in the described Z2 design; Zeloof also reported 1,200 transistors on one piece of silicon in the Z2 array (2021 update). |
| Electrical behavior | not stated in the cited project notes. | Zeloof reported an NMOS threshold voltage of about 1.1 V and compatibility with 2.5 V and 3.3 V logic levels (2021 update). |
| Reported functional samples | Zeloof’s notes say yield can be as high as 80% for the large features involved; this is a conditional process observation, not an independently validated manufacturing-yield study. | Of 15 chips reported made, at least one was completely functional and at least two were mostly functional. Zeloof said proper yield data was not yet available (2021 update). |
The transistor counts describe different things: 100 transistors for the Z2 design and 1,200 reported on one piece of silicon in an array. They should not be treated as interchangeable counts for one finished circuit. The electrical measurements and sample outcomes above are Zeloof’s own reports, not independent qualification results.
What does the fabrication process involve?
The Z1 was not a single pattern-and-etch operation. Zeloof documented four masks—active/doped area, gate oxide, contact window and top metal—and 66 individual fabrication steps. He estimated that a full run took approximately 12 hours. That figure is for the documented Z1 flow, not a general production time for homebuilt chips.
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- Prepare the silicon. Wafers are diced and cleaned before oxidation and photoresist coating.
- Define patterns. A UV lithography setup exposes resist through patterned masks. Zeloof documented a maskless, DLP-style exposure setup and an approximately 365 nm UV epoxy-curing lamp used for photoresist exposure.
- Form device regions. Oxide windows are opened using wet chemical etching or reactive-ion etching. Dopants are introduced by diffusion from solid or liquid sources.
- Add contacts and wiring. Aluminum or another metal is deposited in a vacuum chamber, then patterned and etched to form contacts and interconnects.
- Check the devices. Zeloof initially relied on probing because wire bonding was unavailable. Transistor curves and ring-oscillator behavior served as process checks.
These are stages in a specialized semiconductor process, not instructions for reproducing it. The relevant achievement is integrating the stages into a working lab process, rather than merely having a UV source or an etching vessel.
Why is a homebuilt IC a significant achievement—and what are its limits?
The notable result is process integration: Zeloof assembled cleaning, oxidation, doping, lithography, etching, deposition and testing using improvised or second-hand equipment. Hackaday reports equipment including a DLP projector, tube furnace and vacuum system, as well as dopants sourced from consumer products. That shows that some transistor structures and small circuits can be fabricated outside a commercial foundry. It does not show that a garage process can match foundry-scale alignment, contamination control, repeatability, throughput or yield.
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The Z2’s polysilicon gates brought the reported NMOS behavior described above, but Zeloof also cautioned in his 2021 update that process repeatability and yield remained diminished. The sample report is too small, and the author explicitly said proper yield data was unavailable, to support a reliable statistical yield estimate. The available accounts also do not establish independent replication or a peer-reviewed yield study.
Independent reader supportYour contribution helps us test, update, and keep practical guides available for everyone.Could someone do this with ordinary PCB tools?
No. PCB tools pattern copper on a board; they do not supply the wafer processing needed to form semiconductor devices. The documented work relies on equipment such as a tube furnace, vacuum deposition system and lithography apparatus, along with controlled chemical processing and electrical measurement.
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The chemistry and equipment carry serious hazards, including hydrofluoric acid, strong acids, toxic dopants, high temperatures, vacuum systems and high voltage. A consumer PCB kit is not a safe or technically adequate substitute. The process is best understood as a specialized semiconductor laboratory project, not a casual extension of etching circuit boards.
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